CV

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Education

• Bachelor of Science in Computer Engineering (BSCE)
  • California Polytechnic State University, San Luis Obispo
  • Expected Graduation: June 2025
  • GPA: 3.4
  • Relevant Coursework:
    • Compiler Design
    • Computer Architecture
    • Systems Programming
    • Networks
    • UNIX
    • Embedded Systems
    • FPGA Design
    • Digital Design
    • Electronics
    • Electric Circuit Analysis & Lab I-III

Work experience

• Fluke Corporation | June - September 2024
  • Everett, WA, USA
  • Firmware Engineering Intern
  • Responsibilities:
    • Coordinated with cross-functional teams to design and implement CI/CD automated firmware testing architecture and framework.
    • Worked on Code Synthesis & Validation to translate in-house testing programming language to Python.
    • Developed a source-to-source compiler to remove legacy in-house language and code system.
    • Utilized Agile methodologies to iterate quickly and integrate new developments with both legacy and existing systems.
• Ace Hardware | June 2023 - September 2023
  • Fairfax, CA, USA
  • Employee
• Glumac | June - September 2022
  • San Francisco, CA, USA
  • Electrical Engineering Intern

Skills

• Programming Languages:
  • C, C++, Python, Java, Verilog, VHDL, SystemVerilog, x86 Assembly
• Tools & Technologies:
  • Logic Analyzer, Debugging, Version Control (Git), Microcontrollers, KiCad, Autodesk Eagle, LtSpice, FPGA Design, IC Design, Xilinx Tools
• Methodologies:
  • Agile, Test Driven Development (TDD), Polyhedral and Affine Analysis
• Other Skills:
  • Embedded Systems, Digital Design, Electric Circuit Analysis, Automated Hardware Synthesis

Research

• Dynamic CGRA Accelerator | FPGA, LLVM, AI/ML
  September 2024 - Present
  • Conducting research on dynamic acceleration of processors by mapping instructions spatially.
  • Designed and implemented a Coarse Grained Reconfigurable Array (CGRA) for dynamic instruction acceleration.
  • Implemented an Out-of-Order execution pipelined processor adhering to the RISC-V32i standard.
  • Developing LLVM-based compiler passes to optimize transformations and data mappings for CGRA fabrics.
  • Utilizing polyhedral and affine analysis to optimize dependencies for dataflow-optimized CGRA architecture.
  • Focusing on improving computational efficiency, reducing power consumption, and enhancing control dependencies in dynamic acceleration.

Projects

• Minilang Compiler | Zig, C, Minilang
  March 2024 - June 2024
  GitHub Repository
  • Developed an optimizing compiler from scratch in Zig supporting ARMv8 and LLVM backends.
  • Employed Agile and Test Driven Development methodologies with SSA and stack transformations.
  • Created a custom Intermediate Representation (IR) to facilitate modular backend implementations with per-backend verification steps.
• Arduino ML Accelerator | SystemVerilog, IC Design, FPGA
  February 2023 - March 2023
  • Developed an embedded FPGA ML accelerator for an Arduino Mega over SPI using Xilinx tools.
  • Implemented automated hardware synthesis from a pretrained model in Python.
  • Achieved a 30% reduction in running time for letter classification compared to MCU-only solutions.
• RiskBoy | SystemVerilog, Verilog, RISC-V
  September 2022 - January 2023
  • Implemented a full RISC-V CPU and custom GPU to run games.
  • Developed a custom 5-stage pipeline RISC-V32i processor with 64KB RAM and a 400MHz clock.
  • Created a NES-inspired GPU supporting 640x480 resolution at 60fps with 256 colors in 16 swatches.
  • Integrated components into a handheld unit capable of running games similar to a Game Boy.
• Scroll Scribbler | C/C++, Zephyr/FreeRTOS
  June 2020 - December 2023
  • Designed a 2D CNC machine that writes on scrolls as a printer replacement.
  • Collaborated with a cross-functional team to design and fabricate the chassis and system.
  • Achieved the ability to write a full 8.5”x11” page of text in 10 minutes.
  • Utilized SPI & UART along with a custom communication protocol to enhance image processing throughput.
  • Conducted small-scale test automation and firmware verification & validation.
• 8086 Laptop | C, x86ASM, UNIX
  September 2023 - Present
  • Developing a laptop based around the 8086 chip from the 1970s.
  • Designed and fabricated a custom PCB board layout and design.
  • Developed a custom event-based OS written in C, utilizing Test Driven Development for shift-left testing.
• Pocket Todo | C, Zephyr RTOS, BLE, WiFi
  • August 2024 - Present**
  • A small device to manage my todo lists and time tracking.
  • Developed a portable task management device using an ESP32 with Zephyr RTOS, integrating Wi-Fi connectivity and custom-built time-tracking and to-do web apps.
  • Leveraged Zephyr RTOS drivers for managing system components efficiently, focusing on integration and performance.
  • Utilized Hardware in the loop (HIL) test automation to reduce development time.